Semiconductor memory device
US6646300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2001 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Mar 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.