Grounded body SOI SRAM cell

US6646305B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Fariborz Assaderaghi · Jefferson Valley, US
• Andres Bryant · South Burlington, US
• Peter E. Cottrell · South Burlington, US
• Robert J. Gauthier, Jr. · South Burlington, US
• Randy W. Mann · Jericho, US
• Edward J. Nowak · South Burlington, US
• Jed H. Rankin · South Burlington, US

Key dates

• Filing date: Jul 25, 2001
• Grant date: Nov 11, 2003
• Expiry date: Jul 25, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.