Matched impedance bonding technique in high-speed integrated circuits
US6646343B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2002 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and an integrated circuit package support a high-speed integrated circuit operating at 10 GHz or higher switching speeds. The packaged integrated circuit has external terminals, a semiconductor die having conventional bonding pads, a substrate (e.g., printed circuit board) having conductive traces to couple input, output or bi-directional signals between bonding finger areas of the conductive traces and the external terminals. A ground plate that is electrically isolated from a conductive trace is positioned in the vicinity of the bonding finger area of the conductive trace. Bond wires connect the bonding pads of the electronic circuit and the bonding finger areas of the conductive traces. The ground plate improves integrity in a high-speed signal by canceling the complex impedance of a bond wire. In addition, the packaged integrated circuit can use multiple bond wires to connect the same bonding finger area of a conductive trace on the substrate and a corresponding bonding pad of the electronic circuit. The multiple bond wire approach reduces inductance in the bond wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.