Method and system for reducing hazards in a flip-flop
US6646487B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jan 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.