Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same
US6646936B2 · kind B2 · utility
53Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Mar 12, 2002 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM includes a test mode circuit. Test mode circuit generates respective test mode signals of an L level and an H level by detecting first and second power supply voltages in response to first and second test mode shift signals, respectively. A control circuit controls peripheral circuits to input and output data for executing a special test to and from a plurality of memory cells in response to receiving of the test mode signals of an L level and an H level. Consequently, a semiconductor memory device can enter the test mode in a module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.