Data transfer control device, semiconductor memory device and electronic information apparatus
US6646947B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2002 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jun 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.