Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
US6647081B2 · kind B2 · utility
10Cited by
1References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.