Direct memory access transfer reduction method and apparatus to overlay data on to scatter gather descriptors for bus-mastering I/O controllers
US6647438B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2000 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Dec 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Direct memory access (DMA) transfers to read data from memory are reduced by overlaying data into an immediate data space of a descriptor ring. The descriptor ring includes a context descriptor that points to the data overlaid into the immediate data space. This data space contains smaller blocks of data, such as header or control information for a packet/frame. The descriptor ring further includes scatter gather descriptors that point to data buffers outside of the descriptor ring. These data buffers contain larger blocks of data, such as payload data of the packet/frame. The scatter gather descriptor(s), context descriptor(s), and immediate data space(s) are arranged contiguously in the descriptor ring to allow the descriptor ring to be read in a single direct memory access (DMA) transfer or burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.