Address translation circuit for processors utilizing a single code image
US6647483B1 · kind B1 · utility
7Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Apr 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an offset, (ii) mask the first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare the first masked address with the second masked address, and (v) add the offset to the first address to present a third address in response to the first masked address being at least as great as the second masked address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.