Method for manufacturing semiconductor device having capacitor and via contact
US6649464B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Jul 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for manufacturing semiconductor devices are provided. First and second portions of a first metal layer are formed in a first interlayer insulating layer. A second interlayer insulating layer is formed to cover the first portion and has an opening that exposes the second portion. A dielectric layer is formed on the exposed second portion. A second metal layer is formed on the dielectric layer to fill the opening in a capacitor region. A via contact hole to expose the first portion is formed in the second insulating layer. A third metal layer is formed in the via contact hole. A third interlayer insulating layer is formed on the second interlayer insulating layer. Contact holes to expose the second metal layer and the third metal layer are formed in the third interlayer insulating layer. A fourth metal layer is formed in the contact holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.