Ferroelectric capacitor having upper electrode lamination
US6649954B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 17, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Apr 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
A ferroelectric capacitor adapted for a non-volatile semiconductor memory comprises a base substrate with an insulating surface, such as a semiconductor substrate formed with semiconductor elements and having a top insulator film, a lower electrode formed on the insulating surface, an oxide ferroelectric layer formed on the lower electrode, a first oxide upper electrode formed on and in contact with the upper surface of the oxide ferroelectric layer, and a second oxide upper electrode formed on the first oxide upper electrode, wherein one of the first and second oxide upper electrodes comprises SRO that laminating a first and a second oxide upper electrodes onto said oxide contains at least 0.1 at % additive and the other of the first and second oxide upper electrodes comprises IrOx. A non-volatile semiconductor memory or ferroelectric capacitor, having a PZT ferroelectric layer, excellent in characteristics, and capable of being manufactured efficiently, is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.