Modular collection of spare gates for use in hierarchical integrated circuit design process
US6650139B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2001 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Dec 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are presented for using spare gates to repair logic errors in a digital logic IC with a hierarchical physical design. According to the system and method, the spare gates are organized as scalable modules, consisting of varying numbers of identical sub-modules. The scalable modules are not part of the functional circuitry of the IC, but the spare gates within their sub-modules may be incorporated into faulty functional circuitry to correct the logic error. This is accomplished by altering the metalization layer of the IC to reconnect the spare gates, and does not require changing the physical layout (i.e., adding more pins, relocating gates, etc.) of the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.