Clock generator for integrated circuit
US6650163B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Aug 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/354
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in whi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.