Frequency selective distributed amplifier
US6650185B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Apr 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/605
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency selective differential amplifier (400) consistent with certain embodiments of the invention has a plurality of N amplifier stages (401, 402, 403 through 404) that collectively drive load (410). The plurality of N amplifier stages (401, 402, 403, . . . , 404) have input nodes and output nodes. A plurality of N−1 output phase shift circuits (421, 422, . . . , 423) connect the output nodes of the plurality of amplifier stages in a manner that causes output signals from the plurality of output nodes to add together for delivery to the load (410), the plurality of output phase shift circuits (421, 422, . . . , 423) have a plurality of phase shifts of &thgr;(f)={&thgr;(f)1,2; &thgr;(f)2,3; . . . ; &thgr;(f)N−2,N−1}. A plurality of N−1 input phase shift circuits (431, 432 through 433) are coupled to the plurality of input nodes and provide input signals thereto. The plurality of input phase shift circuits (431, 432, . . . , 433) have a plurality of phase shifts of &PHgr;(f)={&PHgr;(f)1,2; &PHgr;(f)2,3; . . . ; &PHgr;(f)N−2,N−1}. To achieve the frequency selectivity of the current invention, &thgr;(f) is not equal to &PHgr;(f), so that output…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.