Decision directed suppressed carrier symbol-rate PLL with programmable phase discriminator and chip-rate phase extrapolation
US6650187B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop apparatus and method is disclosed. A typical apparatus includes a demodulator receiving a phase error signal from a comparator at a chip rate and providing a phase error update over a symbol period from the phase error signal wherein the chip rate is higher than the symbol rate. A phase discriminator produces a phase error output at the symbol rate from the phase error update based upon a signal modulation type. A loop filter produces one or more phase estimate parameters at a symbol rate from the phase error output and a numerically controlled oscillator (NCO) extrapolates a phase reference at a chip rate from the one or more phase estimate parameters at a symbol rate. The comparator produces the phase error signal to the demodulator based upon the phase reference and an incoming signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.