Quadrature sampling architecture and method for analog-to-digital converters
US6650264B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1999 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Oct 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/47
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Quadrature sampling architecture and method are disclosed for analog-to-digital converters that provide improved digital output signals over prior quadrature mixing implementations. Sampling circuitry according to the present invention samples an input signal with a first and second sampling signals to produce real and imaginary sampled output signals. The first sampling signal, which is associated with the real sampled output signal, is delayed by one-fourth cycle with respect to the second sampling signal, which is associated with the imaginary sampled output signal. This one-fourth cycle sampling signal difference allows for simplified construction of the sampling circuitry. In addition, filter circuitry according to the present invention processes the real and imaginary digital data output signals so that the imaginary digital data output signal is advanced by one-fourth cycle with respect to the real digital data output signal. This one-fourth cycle relative advance tends to eliminate undesirable magnitude distortion and error signals in complex digital output signals that have been mixed down to baseband. Furthermore, the real and imaginary signal paths may be interchanged an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.