Method and architecture for varying power consumption of a current mode digital/analog converter in proportion to performance parameters
US6650265B1 · kind B1 · utility
24Cited by
8References
23Claims
0Family size
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Key dates
| Filing date | Apr 25, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Apr 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuit structure scale the power consumption of a current mode digital/analog converter (DAC) in proportion to performance parameters, such as sampling speed (i.e., clock samples per second) and resolution (number of bits) under programmable control. In one embodiment, a current mode segmented DAC provided approaches the performance of custom implementations designed for specific combinations of these parameters, across a wide range of such parameters by varying current relative to the sampling rate and the resolution and by selectively enabling current sources in the DAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.