Device and method for selecting power down exit
US6650594B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Oct 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit and a memory device capable of selecting power-down exit speed and power-save modes and method thereof are provided. The memory device includes a command decoder for generating a power-down signal in response to a power-down command, a mode register (MRS) for storing power-down exit information, a clock synchronization circuit such as a DLL or PLL circuit for generating an internal clock signal synchronized with an external clock signal, and a controller for controlling the DLL or PLL circuit. At power-down exit of the memory device, the power-down exit information can be selected between a fast wakeup time and a slow wakeup time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.