Secure fast packet switch having improved memory utilization
US6650639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | May 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a secure fast packet switch having a plurality of input ports and a plurality of output ports, a method of determining which port in the plurality of output ports data that is received on one input port in the plurality of input ports is to be sent to, the method including the steps of determining a physical layer address of a sending node, determining a physical layer address of a receiving node, determining an input port in the plurality of input ports that the data was received on, determining if the physical layer address of the sending node and the physical layer address of the receiving node are an allowed combination, determining the magnitude of the node identification number of the sending node, determining the magnitude of the node identification number of the receiving node, obtaining outbound port information from a first predetermined location in a data structure stored in a memory if the node identification number of the sending node is greater than the node identification number of the receiving node, and obtaining outbound port information from a second predetermined location in the data structure stored in the memory if the node identification number of the send…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.