Transmitter architecture having a secondary phase-error correction loop including an amplitude reconstruction system
US6650875B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Dec 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for using a translation loop upconverter and power amplifier including a secondary phase-error correction loop uses the output of the upconverter to lock a feedback loop during a time in which the output of the power amplifier is insufficient to provide feedback to the upconverter. After the power amplifier has developed sufficient power to provide feedback to the upconverter, the feedback to the upconverter is taken from the output of the power amplifier. By placing a phase detector and phase shifter in the secondary feedback path taken from the output of the power amplifier, any phase distortion present in the system can be detected and corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.