Wireless data communications using FIFO for synchronization memory
US6650880B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Jul 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W88/02
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM mic…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.