Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs
US6651088B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1999 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Jul 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a shared memory computer system to reduce the latency times associated with lock/unlock code sequences. The computer system includes a shared memory and a plurality of processors. When one of the processors wishes to modify a shared variable stored in the shared memory, the processor must first request and receive a lock from the shared memory. The lock prevents any other processor in the computer system from modifying data in the shared memory during the locked period. In the present invention, a list of variables in the shared memory that are shared by two or more of the processors is generated. When one of the processors is granted a lock, a prefetch instruction is executed for each variable in the list. Each prefetch instruction specifies the processor receiving the lock as the destination of the data specified in that prefetch instruction. The list may be generated by a compiler during the compilation of a program that is to run on one of the processors. Alternatively, the list can be generated while the program is running either with test data or during the normal execution of the program. The list generation and prefetch instruction executions may be c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.