Multiprocessor system
US6651139B1 · kind B1 · utility
64Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Mar 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a multiprocessor system having plural processors and an optical bus shared by the plural processors, and intends to simplify the cache control, reduce the volume of hardware, and shorten the memory access processing time. For this purpose, the multiprocessor system of the invention includes a shared memory, a cache memory connected to the shared memory, an optical bus connected to the cache memory, and plural processors connected to the optical bus, which access to the cache memory through the optical bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.