Flexible multi-bit per symbol rate encoding
US6651210B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Mar 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention comprises a demultiplexer to divide a bit stream into a first block at a first output and a second block at a second output, a convolutional coder coupled to the first output to encode the first block and a block coder coupled to the second output to encode the second block. The invention further includes a function module coupled to the block coder to apply one of a plurality of different functions to the encoded second block to produce a third block at an output and a mapper coupled to the function module output and to the convolutional coder to map the third block from the output of the function module and the encoded first block into one of a plurality of modulation constellations. A controller is coupled to the demultiplexer to control the size of the first and second blocks, is coupled to the block coder to control the block coding, and is coupled to the function module to control the function to be applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.