Recording/reproduction device, semiconductor memory, and memory card using the semiconductor memory
US6651212B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Jun 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ECC circuit implements a first error correction using a first BCH connection code and flash memory chips implement a second error connection using a second BCH error correction code which uses the same Galois filed. A controller implements error detection based on the first error correction code and using the information provided by the flash memory chip. Upon detecting error, the controller cancles the result of the second error correction made by the flash memory chip based on correction information and information of the error position and error value provided by the flash memory chip. The controller calculates the error position and error value by using the syndrome of the second error correction code derived from the information of computation and the syndrome of first error connection code and implements error correction for the related data based on the calculated error position and error value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.