Programmable multi-level track layout method and system for optimizing ECC redundancy in data storage devices
US6651213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/15
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for adaptively controlling the error correction redundancy is presented. The method utilizes test information collected at the file characterization test to adaptively determine the quantity of error correction code bytes needed at a multitude of levels of the error correction scheme. The error correction needed at the sub-block level is determined from a measurement of the back ground noise floor. At the block level the file characterization is specific to zones identified by head, disk, sector and cylinder. The formatting efficiency of the drive is increased by adaptively linking the length of the error correction code to the location of the zone. By measuring the error rate (E/R) on a per zone basis and comparing this rate to the disk level E/R the ECC can be optimized on a per-zone basis. The method is implemented by modeling a probability distribution as a first polynomial having a basis, converting the first polynomial to a second polynomial having a different basis, and by defining a Hamming distance distribution from the second polynomial. In a preferred embodiment, modeling the probability distribution includes modeling as a Charlier polynomial, and converting to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.