Intent-driven functional verification of digital designs
US6651228B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.