Semiconductor integrated circuit device, and method of placement and routing for such device
US6651236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2001 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Sep 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device fabricated with reduced size and wiring to alleviate wiring delay, and an improved placement and routing method of the building-block type for appropriate use in deep-submicron processes for fabricating such semiconductor device. This semiconductor integrated circuit device includes at least a plurality of integrated circuit blocks to be interconnected by wiring, and a terminal cell including a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in a block netlist. The interconnection among the integrated circuit blocks is carried out by way of the block terminals provided in circumferential edge portions on the block layout and the terminal target of the terminal cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.