Multi-symbol variable length code decoder
US6653955B1 · kind B1 · utility
6Cited by
4References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 9, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.