Method for compensating non-linearity of a sigma-delta analog-to-digital converter
US6653958B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/424
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A2) with quantization at N levels comprising a digital-to-analog converter (24). The method comprises a calibrating step which consists in transforming the multibit sigma-delta analog-to-digital converter (A2) into a sigma-delta analog-to-digital converter with quantization at three levels, then at two levels. The correction values of each level to be corrected are accurately measured. The method also comprises a normal functioning phase which consists, when the sigma-delta an analog-to-digital converter (A2) is operating with quantization at N levels, in producing an instantaneous correction of errors of the analog-to-digital converter (24) using said correction values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.