Method and circuit for reduction of correlated noise
US6653992B1 · kind B1 · utility
9Cited by
10References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Aug 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/616
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for reducing correlated noise in imagers is disclosed. According to an aspect, correlated noise is reduced by coupling the reference inputs of imager amplifiers to common voltage sources. The reference inputs of differential amplifiers on the imager can be coupled to common noise sources such as the imager low gate voltage and array bias voltage through suitably chosen capacitances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.