High-speed flat-panel display interface
US6654066B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/006
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display interface is arranged to processes analog input signals to provide digital output signals. The display interface includes a series of programmable current sources, an input buffer circuit, a first reference buffer circuit, a second reference buffer circuit, and an analog-to-digital converter. The programmable current sources are arranged to provide first and second reference signals, which are buffered by reference buffer circuits and provided to the analog-to-digital converter. The input buffer circuit provides a buffered input signal to the analog-to-digital converter, and operates in an open-loop configuration for improved operating speed. The analog-to-digital converter is configured to provide a digital output signal (DOUT) in response to the buffered input signal. The analog-to-digital converter includes gain and offset settings that are changed by adjusting the progranmnable current sources. The programmable current sources and reference buffer circuits are outside of the input signal path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.