Semiconductor memory device with a self refresh mode
US6654302B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jan 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a self refresh mode may enter the self refresh mode in response to a self refresh set command and may be released from the self-refresh mode in response to a self refresh release command. The self refresh release command may include a plurality of self refresh release commands sequentially executed while a clock enable signal (CKE) is in a clock enable state. In this way, noise on a clock enable signal may not erroneously release the self refresh mode and the reliability of the self refresh mode may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.