Joint maximum likelihood frame and timing estimation for a digital receiver
US6654432B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1998 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jun 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver for receiving a signal stream in a digital radio communication system. The signal stream includes data frames where each frame including a data signal sequence and a synchronizing signal sequence. The communication system synchronizes the receiver by employing the signal stream. The receiver includes a sampling circuit for sampling symbol levels in the synchronizing signal sequence and a synchronization subsystem. The synchronization subsystem utilizes a frame synchronization circuit, a dynamic interpolator and a decision-directed phase tracking mechanism for removing residual frequency and phase offsets. The synchronization subsystem also includes a threshold detection mechanism for comparing values derived from the sampled frame synchronization output with a predefined value which determines whether synchronization has occurred or not. The dynamic interpolator includes a circuit for generating the interpolation coefficients for timing and initial phase estimation, a maximum likelihood timing and phase estimator, and a data interpolation and decimation unit. The estimated timing offset and phase offset in the dynamic interpolator may change for each frame in the signal …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.