Enhanced memory addressing control
US6654646B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jan 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.