Neural network arithmetic apparatus and neutral network operation method
US6654730B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When neuron operations are computed in parallel using a large number of arithmetic units, arithmetic units for neuron operations and arithmetic units for error signal operations need not be provided separately, and a neural network arithmetic apparatus that consumes the bus band less is provided for updating of synapse connection weights. Operation results of arithmetic units and setting information of a master node are exchanged between them through a local bus. During neuron operations, partial sums of neuron output values from the arithmetic units are accumulated by the master node to generate and output a neuron output value, and an arithmetic unit to which neuron operations of the specific neuron are assigned receives and stores the neuron output value outputted from the master node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.