Optimized system and method for parallel leading one/zero anticipation
US6654775B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An optimized system and method for a parallel leading zero anticipation which ascertains “end of run” patterns in parallel. A string representing the operands of the floating-point addition is divided into nibbles of predetermined bit length (normally 4 bits). Each nibble is analyzed for the end of run patterns and the results from this analysis determine whether a run of leading zero's or one's has ended within the nibble, and if there has been an end of run, the location (bit) of the end of run. The highest order nibble that has an end of run provides the higher order bits in the LZA (leading zero anticipator output) value, while the lower two bits of the LZA value are correlated from the location end of run within the nibble, as previously determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.