Dual master device for improved utilization of a processor local bus
US6654836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jan 25, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual master apparatus for mastering a Processor Local Bus (PLB), which is a high-performance, on-chip bus used in many System on Chip (SOC) applications, supporting up to 16 masters. The apparatus includes a first circuit for generating an address phase for read data coupled to the PLB, and a second circuit for generating an address phase for write data coupled to the PLB. The second address phase generating circuit is adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa. The first and second address phase generating circuits can simultaneously process read and write requests. The apparatus also may include circuits for handling read and write data coupled to the first and second address generating circuits, respectively. Further, the apparatus may include circuits for requesting read and write data coupled to the read- and write-data handling circuits, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.