System and method implementing a secondary bus to avoid read data latency
US6654845B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jan 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/30
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method that enhances overall computer system performance by implementing a secondary bus infrastructure to avoid data phase transaction latencies during primary bus information transfers. In accordance with an embodiment of the invention, the system includes a first bus, coupled to a host adapter and a plurality of media adapters, and a second bus, coupled to the host adapter and a select number of media adapters. The host adapter includes a host first bus controller, coupled to the first bus, and a host second bus controller, coupled to the second bus. Each of the media adapters contain a media first bus controller, coupled to the first bus, and a select number of media adapters contain a media second bus controller, coupled to the second bus. In this configuration, information initiated as a multiple data phase transaction is transferred between the host adapter and media adapters over the first bus and information initiated as a single data phase transaction is transferred between the host adapter and the select number of media adapters over the second bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.