Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator
US6654875B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | May 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.