Hardware-level mitigation and DPA countermeasures for cryptographic devices
US6654884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2003 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jan 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/122
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Differential power analysis is a powerful cryptanalytic method that can be used to extract secret keys from cryptographic hardware during operation. To reduce the risk of compromise, cryptographic hardware can employ countermeasures to reduce the amount of secret information that can be deduced by power consumption measurements during processing. Such countermeasures can include balancing circuitry inside a cryptographic hardware device to reduce the amount of variation in power consumption that is correlated to data parameters being manipulated. This can be facilitated by using a constant-Hamming-weight representation when representing and manipulating secret parameters. Low-level operation modules, such as Boolean logic gates, can be built to process input parameters in a manner that balances the number of ON transistors while simultaneously maintaining a data-independent number of transistor transitions during computation. Leakage reduction may be used with other countermeasures, including introducing noise, unrelated to data being processed, into the power measurements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.