Stable clock generation internal to a functional integrated circuit chip
US6654898B1 · kind B1 · utility
30Cited by
16References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | May 8, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus that provide stable clock generation within a functional integrated circuit are disclosed. The functional integrated circuit provides a function other than clock generation, such as a peripheral or interrupt control. Typically, the clock generation is phase-lock loop (PLL) based. The functional integrated circuit also typically provides power savings modes to conserve power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.