Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements
US6654900B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 2000 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Apr 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00039
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals from an input clock signal based on a delay control signal. The processing then continues by producing a first multiple clock signal from a first set of a plurality of delayed clock signals and the input clock signal. The processing then continues by producing a second multiplied clock signal from a second set of the plurality of delayed clock signals, where the second multiplied clock signal is delayed from the first multiplied clock signal in accordance with a delay of at least one of the delayed clock signals. The processing then continues by generating the delayed control signal based on the first multiplied clock signal, where the delay control signal controls delays of the plurality of delayed clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.