Method and apparatus for improving critical path analysis using gate delay
US6654940B2 · kind B2 · utility
3Cited by
1References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Apr 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are novel methods and apparatus for efficiently providing critical path analysis of a design. In an embodiment, an apparatus disclosed can assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and one simulation is required instead of the two generally required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.