Process for manufacturing an isolated-gate transistor with an architecture of the substrate-on-insulator type, and corresponding transistor
US6656782B2 · kind B2 · utility
22Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Feb 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76289
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The source, drain and channel regions are produced in a silicon layer, completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.