Method of manufacturing semiconductor device including a memory area and a logic circuit area
US6656794B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2003 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Jan 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The manufacturing method of the invention performs over etching to remove an upper portion of a conductive layer in a logic circuit area of a semiconductor device, simultaneously with etching out a stopper layer. The method subsequently patterns the conductive layer to form gate electrodes in the logic circuit area. The height of the gate electrodes is lowered, because of the removed upper portion of the conductive layer. In a subsequent process of polishing an insulating layer, even when the polishing rate of the insulating layer is not constant but varied and the insulating layer in the logic circuit area is polished relatively faster than the insulating layer in a memory area, this arrangement of the invention effectively prevents exposure of the gate electrodes in the logic circuit area, prior to exposure of stopper layers in the memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.