Thin-film transistor array and method for manufacturing same
US6657226B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/443
Abstract
A high-quality thin-film transistor array. The gate insulating film below the pixel electrode is etched off in its entirely or along a slit extending along a drain bus line in order to simultaneously remove the residual a-Si produced due to defective patterning. The insulating film is interposed between a drain bus line and a pixel electrode to form a boundary separating layer therebetween. The reject ratio is suppressed by reducing the occurrence of point defects of semi-bright spots, ascribable to capacitative coupling to the pixel electrodes as a result of interconnection of the residual a-Si produced by defective patterning to the drain bus line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.