Semiconductor device with SRAM section including a plurality of memory cells
US6657243B2 · kind B2 · utility
16Cited by
4References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2001 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Aug 31, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.