Semiconductor memory device having memory transistors with gate electrodes of a double-layer stacked structure and method of fabricating the same
US6657251B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
Abstract
A semiconductor memory device has gate electrodes which are formed on a gate insulating film in direct contact therewith and have nitrogen-doped regions on their sides, or gate electrodes which use a nitrogen-doped polysilicon film. The widthwise end portions of the gate electrodes are located outward of the associated end portion of a semiconductor substrate under the gate electrodes and extend over device isolation regions. This structure can suppress a variation in the threshold voltages of memory cells when the semiconductor memory device operates. It is therefore possible to provide a highly reliable nonvolatile semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.