Data transfer on reconfigurable chip
US6657457B1 · kind B1 · utility
66Cited by
8References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Mar 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reconfigurable chip having reconfigurable elements uses an interconnection system which reduces the maximum signal rise and fall time. In one embodiment, the maximum rise and fall time is reduced by providing bypass paths. In another embodiment, buffers are used to reduce signal rise and fall times. Connections between each of the elements are provided by either providing a loop path or by providing bidirectional arrangements of the buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.